Many semiconductors today are primarily one-trick ponies, specializing in particular tasks such as graphics or networking.
But an experimental computer chip under development at the University of Texas instead could be likened to a chameleon, able to change its color — or in this case, function — according to the task at hand.
“It can configure to [perform] very much like a specialized chip” for devices such as cell phones and digital music players, or it could serve as a powerful central processor in a desktop or other general-purpose computer, said Steve Keckler, a UT computer scientist and a leader of the design effort.
Mr. Keckler hopes to have a prototype of the device, which currently exists primarily in software simulations, finished in about a year. He expects a completed chip to be ready for commercialization around 2010.
If the chip works as planned, it will run at a top speed of 10 gigahertz and perform one trillion operations, meaning individual computing tasks, per second. In comparison, Intel Corp.’s current top-speed Pentium 4 processor runs at 3.4 gigahertz and delivers 6.8 billion operations per second. The anticipated performance has led Mr. Keckler and his design team — which includes collaboration with International Business Machines Corp. — to dub the device a “supercomputer on a chip.”
The Defense Advanced Research Projects Agency a Defense Department agency, is funding Mr. Keckler’s effort, as well as efforts under way at the Massachusetts Institute of Technology, Stanford University and the University of Southern California that have similar goals but are taking different approaches.
Darpa program manager Robert Graybill said he considers the preliminary work by Mr. Keckler’s group to be unique, even among the other efforts under way in the agency’s so-called polymorphous chip program.
Mr. Keckler and his team have dubbed their design “Trips,” for Tera-Op Reliable Intelligently Adaptive Processing System. The term tera-op refers to the targeted one trillion operations per second.
Simply put, the system would divide individual processing cores on the chip into tiny sections that could change automatically for several predetermined functions. The idea is that the processing cores would morph — taking graphics or memory configurations, for instance — as instructions flowed in.
Each chip could contain many processing cores, as many as 16, enabling a single chip to perform multiple functions simultaneously while optimizing for each. Conventional chips generally do only one thing at a time.
In addition, this distributed architecture of Mr. Keckler’s design would reduce what is known as clock delays because parts of the chip performing related functions would be in close proximity on a core. Clock delays, a limiting factor in the performance of conventional chips, refer to the decline in computing work done per chip clock cycle as chips are sped up.